SM320C6678-HIREL_15 Datasheet, PDF (1/244 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

SM320C6678-HIREL
SPRS910A—March 2014—Revised April 2014
Multicore Fixed and Floating-Point Digital Signal Processor
Check for Evaluation Modules (EVM): TMS320C6678
1 SM320C6678 Features and Description
1.1 Features
• Eight SMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
– 1.0 GHz C66x Fixed/Floating-Point CPU Core
› 44.8 GMAC/Core for Fixed Point @ 1 GHz
› 22.4 GFLOP/Core for Floating Point @ 1 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 512K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 4096KB MSM SRAM Memory Shared by Eight DSP
C66x CorePacs
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1-Gbps Wire-Speed Throughput at 1.5 MPackets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Peripherals
– Four Lanes of SRIO 2.1
› 1.24/2.5/3.125/5 GBaud Operation Supported Per
Lane
› Supports Direct I/O, Message Passing
› Supports Four 1×, Two 2×, One 4×, and Two 1× +
One 2× Link Configurations
– PCIe Gen2
› Single Port Supporting 1 or 2 Lanes
› Supports Up To 5 GBaud Per Lane¹
› Supports up to 3.125 GBaud Per Lane in Extended
Temperature Range of - 55°C to 115°C
– HyperLink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 25 Gbaud
– Gigabit Ethernet (GbE) Switch Subsystem
› Two SGMII Ports
› Supports 10/100/1000 Mbps Operation
– 64-Bit DDR3 Interface (DDR3-1600)
› 8G Byte Addressable Memory Space
› DDR3 functionally tested for extended
temperature range of - 55°C to 115°C
› Some Noted Parameters Specified for - 40°C to
105°C Only
– 16-Bit EMIF
– Two Telecom Serial Ports (TSIP)
› Supports 1024 DS0s Per TSIP
› Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps
Per Lane
– UART Interface
– I²C Interface
– 16 GPIO Pins
– SPI Interface
– Semaphore Module
– Sixteen 64-Bit Timers
– Three On-Chip PLLs
• Extended Temperature:
– - 55°C to 115°C
1. Ensured only up to -40°C to 105°C.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.