CY5474FCT543T Datasheet, PDF (1/9 Pages) Texas Instruments – 8-Bit Latched Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT543T
SCCS030 - May 1994 - Revised March 2000
8-Bit Latched Registered Transceiver
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.3 ns max. (Com’l)
FCT-A speed at 6.5 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current
Source current
64 mA (Com’l), 48 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
• Separation controls for data flow in each direction
• Back to back latches for storage
• Extended commercial range of −40˚C to +85˚C
Functional Description
The FCT543T octal latched transceiver contains two sets of
eight D-type latches with separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) controls for each set to
permit independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B enable (CEAB) input must be LOW in order to enter
data from A or to take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal on the A-to-B latch
enable (LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their output no longer
change with the A inputs. With CEAB and OEAB both LOW,
the three-stage B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses CEAB, LEAB, and OEAB inputs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Functional Block Diagram
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
OEBA
CEBA
LEBA
Detail A
DQ
LE
QD
LE
Detail A x 7
B₀
B₁
B₂
B₃
B₄
B₅
B₆
B₇
OEAB
CEAB
LEAB
A₀ A₁ A₂ A₃ A₄ A₅ A₆ A₇
CEAB
CEBA
OEAB
LEAB
LEBA
OEBA
B₀ B₁ B₂ B₃ B₄ B₅ B₆ B₇
Pin Configurations
SOIC/QSOP
Top View
LEBA 1
OEBA 2
A₀ 3
A₁ 4
A₂ 5
A₃ 6
A_{4 7}
A₅ 8
A_{6 9}
A₇ 10
CEAB ₁₁
GND ₁₂
24 V_CC
23 CEBA
22 B₀
21 B₁
20 B2
19 B3
18 B4
17 B5
16 B6
15 ^B7
14 ^LEAB
13 ^OEAB
Copyright © 2000, Texas Instruments Incorporated