CD74HC86 Datasheet, PDF (1/6 Pages) Texas Instruments – High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR Gate

Data sheet acquired from Harris Semiconductor
SCHS137
August 1997
CD74HC86,
CD74HCT86
High Speed CMOS Logic
Quad 2-Input EXCLUSIVE OR Gate
[ /Title
(CD74
HC86,
CD74
HCT86
)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
2-Input
EXCL
USIVE
OR
Features
Description
•
Typical Propagation Delay:
C_L = 15pF, T_A = 25^oC
9ns
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The Harris CD74HC86, CD74HCT86 contain four
independent EXCLUSIVE OR gates in one package. They
provide the system designer with a means for
implementation of the EXCLUSIVE OR function. Logic gates
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability to drive 10 LSTTL loads. The 74HCT
logic family is functionally pin compatible with the standard
74LS logic family.
Ordering Information
TEMP. RANGE
PART NUMBER
(^oC)
PACKAGE
CD74HC86E
-55 to 125 14 Ld PDIP
CD74HCT86E
-55 to 125 14 Ld PDIP
CD74HC86M
-55 to 125 14 Ld SOIC
CD74HCT86M
-55 to 125 14 Ld SOIC
PKG.
NO.
E14.3
E14.3
M14.15
M14.15
Applications
• Logical Comparators
• Parity Generators and Checkers
CD54HC86W
CD54HCT86W
CD54HC86H
-55 to 125
-55 to 125
-55 to 125
Wafer
Wafer
Die
• Adders and Subtractors
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
Pinout
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1644.1