CD74HC75 Datasheet, PDF (1/8 Pages) Texas Instruments – Dual 2-Bit Bistable Transparent Latch

Data sheet acquired from Harris Semiconductor
SCHS135
March 1998
CD74HC75,
CD74HCT75
Dual 2-Bit Bistable
Transparent Latch
[ /Title
(CD74
HC75,
CD74
HCT75
)
/Sub-
ject
(Dual
2-Bit
Bistabl
e
Features
• True and Complementary Outputs
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Description
The Harris CD74HC75 and CD74HCT75 are dual 2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs (1E and 2E) which are
active LOW. When the Enable input is HIGH data enters the
latch and appears at the Q output. When the Enable input
(1E and 2E) is LOW the output is not affected.
Ordering Information
Pinout
CD74HC75, CD74HCT75
(PDIP, SOIC)
TOP VIEW
1Q0 1
1D0 2
1D1 3
2E 4
V_CC 5
2D0 6
2D1 7
2Q1 8
16 1Q0
15 1Q1
14 1Q1
13 1E
12 GND
11 2Q0
10 2Q0
9 2Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 1666.1