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CD74FCT573 Datasheet, PDF (1/7 Pages) Texas Instruments – BiCMOS FCT Interface Logic, Octal Transparent Latches, Three-State
CD74FCT573AT was not acquired from Harris Semiconductor.
CD74FCT573,
Data sheet acquired from Harris Semiconductor
SCHS260A
January 1997
Features
• Buffered Inputs
NOFOUTsRRe ECNCMEOOWSMDTMeEcEhSNnIoGDloNEgSDy
• TTAyp=ic2a5loPCro, CpaLg=at5i0opnFD(eClaDy7:43F.C9nTs57a3tAVTC)C = 5V,
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• FCTXXX Types
- Speed of Bipolar FAST™/AS/S
• FCTXXXAT Types
- 30% Faster than FAST™/AS/S with Significantly
Reduced Power Consumption
• 48mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output Edge Rates
• Input/Output Isolation to VCC
• BiCMOS Technology with Low Quiescent Power
CD74FCT573AT
BiCMOS FCT Interface Logic,
Octal Transparent Latches, Three-State
Description
The CD74FCT573 and CD74FCT573AT octal transparent
latches use a small geometry BiCMOS technology. The out-
put stage is a combination of bipolar and CMOS transistors
that limits the output HIGH level to two diode drops below
VCC. This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
VCC bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
48 milliamperes.
The CD74FCT573 and CD74FCT573AT outputs are trans-
parent to the inputs when the Latch Enable (LE) is HIGH.
When the Latch Enable (LE) goes LOW, the data is latched.
The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in
the high impedance state. The latch operation is indepen-
dent of the state of the Output Enable.
Ordering Information
PART NUMBER
TEMP.
RANGE (oC) PACKAGE
PKG.
NO.
CD74FCT573ATE
0 to 70 20 Ld PDIP E20.3
CD74FCT573M
0 to 70 20 Ld SOIC M20.3
CD74FCT573SM
0 to 70 20 Ld SSOP M20.209
NOTE: When ordering the suffix M and SM packages, use the entire
part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD74FCT573, CD74FCT573AT
(PDIP, SOIC, SSOP)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-1
File Number 2304.2