CD74FCT244M96 Datasheet, PDF (1/11 Pages) Texas Instruments – BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS

D BiCMOS Technology With Low Quiescent
Power
D Buffered Inputs
D Noninverted Outputs
D Input/Output Isolation From V_CC
D Controlled Output Edge Rates
D 64-mA Output Sink Current
D Output Voltage Swing Limited to 3.7 V
D SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
description/ordering information
CD74FCT244, CD74FCT244AT
BiCMOS OCTAL BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCBS722B – JULY 2000 – REVISED AUGUST 2003
CD74FCT244 . . . E, M, OR SM PACKAGE
CD74FCT244AT . . . E OR M PACKAGE
(TOP VIEW)
1OE 1
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 V_CC
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
The CD74FCT244 and CD74FCT244AT are octal
buffer/line drivers with 3-state outputs using a
small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that
limit the output high level to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V)
reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and
ground bounce and their effects during simultaneous output switching. The output configuration also enhances
switching speed and is capable of sinking 64 mA.
These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74FCT244E
CD74FCT244E
0°C to 70°C
SOIC – M
SSOP – SM
Tube
Tape and reel
Tape and reel
CD74FCT244M
CD74FCT244M96
CD74FCT244SM96
74FCT244M
FCT244SM
PDIP – E
Tube
CD74FCT244ATE
CD74FCT244ATE
SOIC – M
Tube
Tape and reel
CD74FCT244ATM
CD74FCT244ATM96
74FCT244ATM
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
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