CD54-74FCT240 Datasheet, PDF (1/3 Pages) Texas Instruments – FCT Interface Logic Octal Buffers/Line Drivers, Three-State

CD74FCT240AT and CD74FCT244AT were not acquired from Harris Semiconductor.
Data sheet acquired from Harris Semiconductor
SCHS270A
February 1996
CD54/74FCT240, CD54/74FCT240AT,
CD54/74FCT241, CD54/74FCT244,
CD54/74FCT244AT
FCT Interface Logic
Octal Buffers/Line Drivers, Three-State
Features
Description
• CD54/74FCT240, CD54/74FCT240AT - Inverting
• CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT -
Non-Inverting
• Buffered Inputs
• Typical Propagation Delay:
4.1ns at VCC = 5V, TA = 25^oC (FCT240AT, FCT244AT)
• SCR-Latchup-Resistant BiCMOS Process and Circuit
Design
• FCTXXX Types - Speed of Bipolar FAST®/AS/S;
FCTXXXAT Types - 30% Faster Than FAST/AS/S with
Significantly Reduced Power Consumption
• 48mA to 64mA Output Sink Current (Commer-
cial/Extended Industrial)
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output-Edge Rates
• Input/Output Isolation to VCC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
PART NUMBER
CD54/74FCT240E
CD54/74FCT240ATE
CD54/74FCT241E
CD54/74FCT244E
CD54/74FCT244ATE
CD54/74FCT240M
CD54/74FCT240ATM
CD54/74FCT241M
CD54/74FCT244M
CD54/74FCT244ATM
CD54/74FCT240SM
CD54/74FCT241SM
CD54/74FCT244SM
CD54FCT240H
CD54FCT241H
CD54FCT244H
TEMP. RANGE (^oC)
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125, 0 to 70
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SSOP
20 Ld SSOP
20 Ld SSOP
The CD54/74FCT240, 240AT, 241, 244 and 244AT three-
state octal buffers/line drivers use a small-geometry
BiCMOS technology. The output stage is a combination of
bipolar and CMOS transistors that limits the output-HIGH
level to two diode drops below VCC. This resultant lowering
of output swing (0V to 3.7V) reduces power bus ringing (a
source of EMI) and minimizes VCC bounce and ground
bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48mA to 64mA.
The CD54/74FCT240, 240AT, 244 and 244AT have active-
LOW output enables (1OE, 2OE). The CD54/74FCT241 and
CD54/74FCT241AT have one active-LOW (1OE) and one
active-HIGH (2OE) output enable.
Functional Diagram
1A0
2
1A1
4
1A2
6
1A3
8
2A0 ¹¹
2A1 ¹³
2A2 ¹⁵
2A3 ¹⁷
240, 244 241
1OE 1OE
1 19
2OE 2OE
241, 244 240
18 _{1Y0 1Y0}
16 _{1Y1 1Y1}
14 _{1Y2 1Y2}
12 _{1Y3 1Y3}
9
2Y0 2Y0
7
2Y1 2Y1
5
2Y2 2Y2
3
2Y3 2Y3
VCC = 20
GND = 10
CD54/74FCT240, CD54/74FCT240AT TRUTH TABLE
INPUT
INPUT
OUTPUT
1OE, 20E
A
Y
L
L
H
L
H
L
H
X
Z
CD54/74FCT244, CD54/74FCT244AT TRUTH TABLE
INPUT
INPUT
OUTPUT
1OE, 2OE
A
Y
L
L
H
L
H
L
H
X
Z
CD54/74FCT241 TRUTH TABLE
INPUT
1OE
1A
OUTPUT
1Y
INPUT
2OE
2A
L
L
L
L
X
L
H
H
H
L
H
X
Z
H
H
OUTPUT
2Y
Z
L
H
NOTE: H = High Voltage Level, L = LOW Voltage Level
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
X = Immaterial, Z = HIGH Impedance
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
1
File Number 2227.3