BQ2204A Datasheet, PDF (1/12 Pages) Texas Instruments – X4 SRAM Nonvolatile Controller Unit

bq2204A
X4 SRAM Nonvolatile Controller Unit
Features
ä Power monitoring and switching
for 3-volt battery-backup applica-
tions
ä Write-protect control
ä 2-input decoder for control of up
to 4 banks of SRAM
ä 3-volt primary cell inputs
ä Less than 10ns chip-enable
propagation delay
ä 5% or 10% supply operation
General Description
The CMOS bq2204A SRAM Non-
volatile Controller Unit provides all
necessary functions for converting
up to four banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the 5V
VCC input for an out-of-tolerance condi-
tion. When out-of-tolerance is detected,
the four conditioned chip-enable outputs
are forced inactive to write-protect up to
four banks of SRAM.
During a power failure, the external
SRAMs are switched from the V_CC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAMs are write-protected until a
power-valid condition exists.
During power-valid operation, a
two-input decoder transparently se-
lects one of up to four banks of
SRAM.
Pin Connections
VOUT
1
BC2
2
NC
3
A
4
B
5
NC
6
THS
7
VSS
8
16
VCC
15
BC1
14
CE
13
CECON1
12
CECON2
11
CECON3
10
CECON4
9
NC
16-Pin Narrow DIP or SOIC
PN220401.eps
Pin Names
VOUT
Supply output
BC1–BC2 3 volt primary backup cell inputs
THS
Threshold select input
CE
chip-enable active low input
CECON1– Conditioned chip-enable outputs
CECON4
A–B
Decoder inputs
NC
No connect
VCC
+5 volt supply input
VSS
Ground
Functional Description
Up to four banks of CMOS static RAM can be battery-
backed using the V_OUT and conditioned chip-enable out-
put pins from the bq2204A. As VCC slews down during
a power failure, the conditioned chip-enable outputs
CECON1 through CECON4 are forced inactive independ-
ent of the chip-enable input CE.
This activity unconditionally write-protects the external
SRAM as VCC falls below an out-of-tolerance threshold
V_PFD. V_PFD is selected by the threshold select input pin,
THS. If THS is tied to V_SS, the power-fail detection occurs
at 4.62V typical for 5% supply operation.
If THS is tied to V_CC, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to VSS or VCC for proper operation.
If a memory access is in process to any of the four external
banks of SRAM during power-fail detection, that memory
cycle continues to completion before the memory is write-
protected. If the memory cycle is not terminated within
time tWPT, all four chip-enable outputs are unconditionally
driven high, write-protecting the controlled SRAMs.
Dec. 1992 B
1