BQ2203A Datasheet, PDF (1/12 Pages) Texas Instruments – NV Controller With Battery Monitor

bq2203A
NV Controller With Battery Monitor
Features
ä Power monitoring and switching
for nonvolatile control of SRAMs
ä Write-protect control
ä Battery-low and battery-fail indi-
cators
ä Reset output for system power-on
reset
ä Input decoder for control of up to
2 banks of SRAM
ä 3-volt primary cell input
ä 3-volt rechargeable battery in-
put/output
General Description
The CMOS bq2203A SRAM Nonvolatile
Controller With Battery Monitor pro-
vides all the necessary functions for con-
verting one or two banks of standard
CMOS SRAM into nonvolatile
read/write memory. The bq2203A is
compatible with the Personal Computer
Memory Card International Association
(PCMCIA) recommendations for
battery-backed static RAM memory
cards.
A precision comparator monitors the 5V
VCC input for an out-of-tolerance condi-
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect
banks of SRAM.
Power for the external SRAMs is
switched from the VCC supply to the
battery-backup supply as VCC de-
cays. On a subsequent power-up, the
VOUT supply is automatically
switched from the backup supply to
the VCC supply. The external SRAMs
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system. The battery
monitor indicates battery-low and
battery-fail conditions.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
Pin Connections
VOUT
1
BCP
2
NC
3
A
4
BCF
5
NC
6
THS
7
VSS
8
16
VCC
15
BCS
14
CE
13
CECON1
12
CECON2
11
BCL
10
RST
9
NC
16-Pin Narrow DIP or SOIC
PN220301.eps
Pin Names
VOUT
RST
THS
CE
CECON1,
CECON2
A
BCF
BCL
BCP
BCS
NC
VCC
VSS
Supply output
Reset output
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
Bank select input
Battery fail push-pull output
Battery low push-pull output
3V backup supply input
3V rechargeable backup supply input/output
No connect
5-volt supply input
Ground
Functional Description
Two banks of CMOS static RAM can be battery-backed us-
ing the VOUT and the conditioned chip-enable output pins
from the bq2203A. As the voltage input VCC slews down
during a power failure, the two conditioned chip-enable
outputs, CECON1 and CECON2, are forced inactive
independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM
as VCC falls to an out-of-tolerance threshold VPFD. VPFD is
selected by the threshold select input pin, THS. If THS is
tied to VSS, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
Nov. 1994 B
If THS is tied to VCC, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to VSS or VCC for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time tWPT (150µs maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
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