AM3894CCYG120 Datasheet, PDF (1/308 Pages) Texas Instruments – AM389x Sitara ARM Processors

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AM389x Sitara™
ARM^® Processors
Check for Samples: AM3894, AM3892
AM3894
AM3892
SPRS681E – OCTOBER 2010 – REVISED JULY 2012
1 Device Summary
1.1 Features
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• High-Performance Sitara™ ARM^® Processors
– Simultaneous SD and HD Analog Output
– ARM^® Cortex™-A8 RISC Processor
• Up to 1.35 GHz
• ARM^® Cortex™-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Processor Core
• NEON™ Multimedia Architecture
– Supports Integer and Floating Point (VFPv3-
IEEE754 compliant)
– Digital HDMI 1.3 transmitter with PHY with
HDCP up to 165-MHz pixel clock
– Advanced Video Processing Features Such
as Scan/Format/Rate Conversion
– Three Graphics Layers and Compositors
• Dual 32-bit DDR2/3 SDRAM Interfaces
– Supports up to DDR2-800 and DDR3-1600
– Up to Eight x8 Devices Total
– 2 GB Total Address Space
• Jazelle^® RCT Execution Environment
– Dynamic Memory Manager (DMM)
• ARM^® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 256K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• 512K-Bytes On-Chip Memory Controller
(OCMC) RAM
• SGX530 3D Graphics Engine (available only on
the AM3894 device)
– Delivers up to 30 MTriangles/s
– Universal Scalable Shader Engine
– Direct3D^® Mobile, OpenGL^® ES 1.1 and 2.0,
OpenVG™ 1.1, OpenMax™ API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– ARM Instructions/Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165 MHz HD Video Capture Channels
• One 16/24-bit and One 16-bit Channel
• Each Channel Splittable Into Dual 8-bit
Capture Channels
– Two 165 MHz HD Video Display Channels
• One 16/24/30-Bit and One 16-bit Channel
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• Programmable Multi-Zone Memory
Mapping and Interleaving
• Enables Efficient 2D Block Accesses
• Supports Tiled Objects in 0°, 90°, 180°, or
270 Orientation and Mirroring
• Optimizes Interlaced Accesses
• One PCI Express^® (PCIe^®) 2.0 Port With
Integrated PHY
– Single Port With 1 or 2 Lanes at 5.0 GT/s
– Configurable as Root Complex or Endpoint
• Serial ATA (SATA) 3.0 Gbps Controller With
Integrated PHYs
– Direct Interface for Two Hard Disk Drives
– Hardware-Assisted Native Command
Queuing (NCQ) from up to 32 Entries
– Supports Port Multiplier and Command-
Based Switching
• Two 10/100/1000 Mbps Ethernet MACs (EMAC)
– IEEE 802.3 Compliant (3.3V I/O Only)
– MII and GMII Media Independent I/Fs
– Management Data I/O (MDIO) Module
• Dual USB 2.0 Ports With Integrated PHYs
– USB 2.0 High-/Full-Speed Client
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Sitara, SmartReflex, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.
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Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
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ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.
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USSE, POWERVR are trademarks of Imagination Technologies Limited.
5
OpenVG, OpenMax are trademarks of Khronos Group Inc.
6
Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.
7
I²C BUS is a registered trademark of NXP B.V. Corporation Netherlands.
8
PCI Express, PCIe are registered trademarks of PCI-SIG.
9
OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other
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countries.
All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated