THC63LVD823B Datasheet, PDF (9/21 Pages) THine Electronics, Inc. – 160MHz 51Bits LVDS Transmitter

THC63LVD823B_Rev.3.1_E
AC Timing Diagrams
V_diff=(TA+)-(TA-)
80%
TA+
V_diff
5pF _100Ω
20%
TA-
LVDS Output Load
t_LVT
Fig2. LVDS Output Load and Transition Time
80%
20%
t_LVT
CLKIN
/PDWN
2.0V
TCLKx+/-
x=1,2
t_TPLL
Fig3. PLL Lock Time
V_diff=0V
CLKIN
t_TCIP
t_DEINT
DE
t_DEH
t_DEL
Note: In single-in/dual-out, DDR off mode (MODE<1:0>=HL, DDRN =Open or H),
the period between rising edges of DE (t_DEINT), high time of DE (t_DEH)
should always satisfy following equations.
t_DEH = tTCIP * (2m)
t_DEINT = tTCIP * (2n)
m, n =integer
Fig3-1. Single IN / Dual OUT, DDR off mode DE input timing
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THine Electronics, Inc.