THC63LVD823B Datasheet, PDF (3/21 Pages) THine Electronics, Inc. – 160MHz 51Bits LVDS Transmitter

THC63LVD823B_Rev.3.1_E
Pin Description
Pin Name
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
Pin #
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
TCLK2+, TCLK2-
29, 30
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKIN
60 -57, 54 - 51
68 - 61
78 - 73, 70, 69
86 - 79
96 - 89
6, 5, 2, 1,
100 - 97
9
8
7
10
R/F
11
RS
12
MAP
14
MODE1, MODE0
15, 16
Type
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Description
The 1st Link.
The 1st pixel output data when Dual-Link.
LVDS Clock Out for 1st and 2nd Link.
The 2nd Link.
These pins are disabled when Single Link.
Additional LVDS Clock Out. Identical to TCLK1+,-.
No connect if not used.
The 1st Pixel Data Inputs.
The 2nd Pixel Data Inputs.
Data Enable Input.
Vsync Input.
Hsync Input.
Clock Input.
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
LVDS swing mode, V_REF select. See Fig4 - 5.
RS
LVDS
Swing
Small Swing
Input Support
V_IHM
350mV
N/A
V_IMM
350mV
RS=V_REFa
V_ILM
200mV
N/A
a. V_REF is Input Reference Voltage.
LVDS mapping table select. See Fig7 to 8 and Table4 to 7.
MAP
V_IHM
V_ILM
V_IMM
Mapping Mode
Mapping MODE1
Mapping MODE2
Reserved
Pixel Data Mode.
MODE
1
MODE0
L
L
H
L
L
H
H
H
Mode
Dual Link (Dual-in/Dual-out)
Dual Link (Single-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.