THC63LVDM83C-5S Datasheet, PDF (8/13 Pages) THine Electronics, Inc. – REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE

THC63LVDM83C(5S)_Rev.1.10_E
Switching Characteristics
Symbol
t_TCIT
t_TCP
t_TCH
t_TCL
t_TCD
t_TS
t_TH
t_LVT
t_TOP1
Parameter
CLK IN Transition time
CLK IN Period
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/- Delay
TTL Data Setup to CLK IN
TTL Data Hold from CLK IN
LVDS Transition Time
Output Data Position0 (T=11.7ns)
t_TOP0 Output Data Position1 (T=11.7ns)
t_TOP6 Output Data Position2 (T=11.7ns)
t_TOP5 Output Data Position3(T=11.7ns)
t_TOP4 Output Data Position4 (T=11.7ns)
t_TOP3 Output Data Position5 (T=11.7ns)
t_TOP2
t_TPLL
Output Data Position6 (T=11.7ns)
Phase Lock Loop Set
Min.
11.7
0.35T
0.35T
2.5
0
-0.2
T-7-- _{– 0.2}
2T-7-- – 0.2
3T-7-- – 0.2
4T-7-- – 0.2
5T-7-- – 0.2
6T-7-- – 0.2
V_CC = VCC = PLL VCC = LVDS VCC
Typ.
Max.
Units
5.0
ns
T
125
ns
0.5T
0.65T
ns
0.5T
0.65T
ns
3T
ns
ns
ns
0.6
1.5
ns
0.0
+0.2
ns
T-7-
T-7-- _{+ 0.2}
ns
2 ^T-7--
2T-7-- + 0.2
ns
3 ^T-7--
3T-7-- + 0.2
ns
4 ^T-7--
4T-7-- + 0.2
ns
5 ^T-7--
5T-7-- + 0.2
ns
6 ^T-7--
6T-7-- + 0.2
ns
10.0
ms
AC Timing Diagrams
TTL Input
90%
CLK IN _10%
90%
10%
t _TCIT
t _TCIT
Fig2. CLKIN Transition Time
LVDS Output
V_{di ff}=(TA+ )-(TA-)
TA+
V_{d if f}
5pF ₁₀₀
TA-
LVDS Output Load
80%
20%
t_LVT
80%
20%
t _LVT
Fig3. LVDS Output Load and Transition Time
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