THCS133 Datasheet, PDF (7/10 Pages) THine Electronics, Inc. – No External Clock Required.

THCS133_Rev.1.00_E
8bit Output + Output Enable
Upper Output Enable
（CTL1）
Lower Output Enable
（CTL0）
tWOE
tPZO
tCLOE
tPOZ
Data Output
(DATA[7:0])
Upper 8bit data
Lower 8bit data
When receiving new incoming data during CTL0 or CTL1 = Low, output data is updated to this new data.
・Latch Enable, Output Enable Truth Table
Transmitter mode
CTL1
CTL0
Latch Enable Input
Lower 8bit data is transmitted by sampling frequency
L
L
(8bit through mode)
↑
H
Upper 8bit input latch
H
↑
Lower 8bit input latch and 16-bit data reception
H
H
Keep data
The rising edge of CTL0 is the trigger for sampling of upper and lower data.
CTL1
L
L
H
H
CTL0
L
H
L
H
Receiver mode
Output Enable Input
Output disable
（DATA pins are pulled down by 250kΩ internally）
Upper 8bit Output enable
Lower 8bit Output enable
Output disable
（DATA pins are pulled down by 250kΩ internally）
・Transmitter or Receiver select
Pin
RXEN
H
L
Description
Receiver mode (Serial to Parallel)
Transmitter mode (Parallel to Serial)
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