THCS133 Datasheet, PDF (6/10 Pages) THine Electronics, Inc. – No External Clock Required.

THCS133_Rev.1.00_E
Transmitter Mode
Internal Register
Input (DATA[15:0])
Internal Sampling Clock
Serial Data Output
Parallel Input[15:0]
1/fPSPL
tPS
Serial Output
Serial Output
Receiver Mode
Serial Data Input
Internal Register
Output (DATA[15:0])
Serial Input
Serial Input
Parallel Output[15:0]
tSP
Internal sampling clock and CTL signals are asynchronous.
Electrical Characteristics AC Characteristics (Latch Enable, Output Enable)
Symbol
Parameter
Condition
tWLE Latch Enable Pulse Width
-
tSULE Latch Enable Rise Edge Setup Time
-
tHLE Latch Enable Rise Edge Hold Time
-
tCLLE1 Latch Enable Clearance1
-
tCLLE2 Latch Enable Clearance2
-
tWOE Output Enable Pulse Width
-
tCLOE Output Enable Clearance
-
tPZO Output Enable Delay Time
CL=25pF
tPOZ Output Disable Delay Time
CL=25pF
Min Typ Max Unit
130 -
-
ns
133 -
-
ns
20 -
-
ns
100 -
-
ns
20 -
-
us
50 -
-
ns
50 -
-
ns
-
- 50 ns
-
- 38 ns
Timing Chart (Latch Enable, Output Enable)
8bit Input + Latch Enable
tWLE
tCLLE2
Upper Latch Enable
（CTL1）
Lower Latch Enable
（CTL0）
tCLLE1
tSULE
tHLE
Data Input
(DATA[7:0])
Upper 8bit data
Lower 8bit data
Upper 8bit data
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