THC63LVDM83E Datasheet, PDF (7/13 Pages) THine Electronics, Inc. – SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER

THC63LVDM83E_Rev.1.30_E
LV-CMOS/TTL & LVDS Transmitter AC Specifications
Symbol
Parameter
Min
t_TCIT CLK IN Transition Time
t_TCP CLK IN Period
t_TCH CLK IN High Time
t_TCL CLK IN Low Time
t_TCD CLK IN to TCLK+/- Delay
t_TS LV-CMOS/TTL Data Setup to CLK IN
t_TH LV-CMOS/TTL Data Hold from CLK IN
t_LVT LVDS Transition Time
t_TOP1 Output Data Position0 (T=6.25ns ~ 20ns)
t_Top0 Output Data Position1 (T=6.25ns ~ 20ns)
t_Top6 Output Data Position2 (T=6.25ns ~ 20ns)
t_Top5 Output Data Position3 (T=6.25ns ~ 20ns)
t_Top4 Output Data Position4 (T=6.25ns ~ 20ns)
t_Top3 Output Data Position5 (T=6.25ns ~ 20ns)
t_Top2 Output Data Position6 (T=6.25ns ~ 20ns)
t_TPLL Phase Lock Loop Set
*Typ values are at VCC=3.3V, Ta = +25ºC
6.25
0.35T
0.35T
2.0
0.0
-0.15
T/7-0.15
2T/7-0.15
3T/7-0.15
4T/7-0.15
5T/7-0.15
6T/7-0.15
VCC = 3.0~3.6V, Ta= 0~+70ºC
Typ
Max
Units
5.0
ns
T
125
ns
0.5T
0.65T
ns
0.5T
0.65T
ns
3T
ns
ns
ns
0.6
1.5
ns
0.0
+0.15
ns
T/7
T/7+0.15
ns
2T/7 2T/7+0.15
ns
3T/7 3T/7+0.15
ns
4T/7 4T/7+0.15
ns
5T/7 5T/7+0.15
ns
6T/7 6T/7+0.15
ns
10.0
ms
LV-CMOS/TTL Input
90%
CLK IN _10%
90%
10%
t_TCIT
t_TCIT
Fig.3 CLKIN Transmission Time
LVDS Output
V_Diff = (TA+) – (TA-)
TA+
5pF _100Ω
TA-
LVDS Output Load
V_{d if f}
80%
20%
80%
20%
t_LVT
t_LVT
Fig.4 LVDS Output Load and Transmission Time
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THine Electronics, Inc.