THC63LVDF84B_16 Datasheet, PDF (7/16 Pages) THine Electronics, Inc. – 24bit COLOR LVDS RECEIVER (Falling Edge Clock)

THC63LVDF84B_Rev.5.11_E
LVCMOS & LVDS Receiver AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Unit
tRCP
CLKOUT
Transition Time
VCC = 2.5V to 2.7V
VCC = 2.7V to 3.0V
VCC = 3.0V to 3.6V
14.3
14.3
11.8
T
T
T
50.0
66.6
ns
66.6
tRCH
CLKOUT High Time
-
4T/7
-
ns
tRCL
CLKOUT Low Time
-
3T/7
-
ns
tRCD
RCLK IN to CLKOUT +/- Delay
-
5T/7
-
ns
t_RS
LVCMOS Data Setup to CLKOUT
0.35T - 0.3
-
-
ns
tRH
LVCMOS Data Hold from CLKOUT
0.45T – 1.6
-
-
ns
tTLH
LVCMOS Low to High Transition Time
-
2.0
3.0
ns
tTHL
LVCMOS High to Low Transition Time
-
1.8
3.0
ns
tRIP1
Input Data Position0 (T=11.76ns)
-0.4
0.0
+0.4
ns
t_RIP0
Input Data Position1 (T=11.76ns)
T/7-0.4
T/7
T/7+0.4
ns
tRIP6
Input Data Position2 (T=11.76ns)
2T/7-0.4
2T/7
2T/7+0.4
ns
tRIP5
Input Data Position3 (T=11.76ns)
3T/7-0.4
3T/7
3T/7+0.4
ns
tRIP4
Input Data Position4 (T=11.76ns)
4T/7-0.4
4T/7
4T/7+0.4
ns
tRIP3
Input Data Position5 (T=11.76ns)
5T/7-0.4
5T/7
5T/7+0.4
ns
t_RIP2
Input Data Position6 (T=11.76ns)
6T/7-0.4
6T/7
6T/7+0.4
ns
tRPLL
Phase Lock Loop Set
-
-
10.0
ms
*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 7. LVCMOS & LVDS Receiver AC Specifications
LVCMOS Output
Figure 6. CLKOUT Transmission Time
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