THC63LVDF84B_16 Datasheet, PDF (10/16 Pages) THine Electronics, Inc. – 24bit COLOR LVDS RECEIVER (Falling Edge Clock)

THC63LVDF84B_Rev.5.11_E
LVDS Data Timing Diagram
Figure 9. LVDS Data Timing Diagram
Pixel Data Mapping for JEIDA Format (6bit, 8bit Application)
TX Pin
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
6bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
-
-
-
-
-
-
-
8bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
R0
R1
G0
G1
B0
B1
N/A
RX Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 8. Data Mapping for JEIDA Format
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