THC63LVDF84B-5S Datasheet, PDF (6/11 Pages) THine Electronics, Inc. – LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER(Falling Edge Clock)

THC63LVDF84B(5S) _Rev.1.10_E
Switching Characteristics
Symbol
t_RCP
t_RCH
t_RCL
t_RCD
t_RS
t_RH
t_TLH
t_THL
t_RIP1
t_RIP0
t_RIP6
t_RIP5
t_RIP4
t_RIP3
t_RIP2
t_RPLL
Parameter
CLK OUT Period
CLK OUT High Time
CLK OUT Low Time
RCLK +/- to CLK OUT Delay
TTL Data Setup to CLK OUT
TTL Data Hold from CKL OUT
TTL Low to High Transition Time
TTL High to Low Transition Time
Input Data Position0 (T = 11.76ns)
Input Data Position1 (T = 11.76ns)
Input Data Position2 (T = 11.76ns)
Input Data Position3 (T = 11.76ns)
Input Data Position4 (T = 11.76ns)
Input Data Position5 (T = 11.76ns)
Input Data Position6 (T = 11.76ns)
Phase Lock Loop Set
AC Timing Diagrams
TTL Output
Min.
15.4
0.35T-0.3
0.45T-1.6
-0.4
T/7-0.4
2T/7-0.4
3T/7-0.4
4T/7-0.4
5T/7-0.4
6T/7-0.4
V_CC =VCC = PLL VCC = LVDS VCC
Typ.
Max.
Units
T
50.0
ns
4T/7
ns
3T/7
ns
5T/7
ns
ns
ns
2.0
3.0
ns
1.8
3.0
ns
0.0
+0.4
ns
T/7
T/7+0.4
ns
2T/7
2T/7+0.4
ns
3T/7
3T/7+0.4
ns
4T/7
4T/7+0.4
ns
5T/7
5T/7+0.4
ns
6T/7
6T/7+0.4
ns
10.0
ms
8pF
TTL Output Load
TTL Output
80%
20%
t_TLH
80%
20%
t_THL
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