THC63LVDF84B-5S Datasheet, PDF (2/11 Pages) THine Electronics, Inc. – LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER(Falling Edge Clock)

THC63LVDF84B(5S)_Rev.1.10_E
THC63LVDF84B(5S)
LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER(Falling Edge Clock)
General Description
The THC63LVDF84B(5S) receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 28bits of CMOS/TTL data with falling edge
clock.
At a transmit clock frequency of 65MHz, 24bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 1.8Gbps.
Features
• Wide dot clock range: 20-65MHz suited for VGA,
SVGA and XGA
• PLL requires No external components
• Low power consumption
• Power-Down Mode
• Low profile 56 Lead TSSOP Package
• Pin compatible with THC63LVDF84A
Block Diagram
THC63LVDF84B(5S)
RA +/-
DATA
(LVDS)
RB +/-
RC +/-
RD +/-
7 _RA0-6
7 _RB0-6
7 _RC0-6
7 _RD0-6
CMOS/TTL
OUTPUT
CLOCK
(LVDS)
RCLK +/-
20 to 65MHz
RECEIVER
PLL
CLOCK OUT
(20 to 65MHz)
/PDWN
(140-455Mbit/On Each LVDS Channel)
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