THC63LVD823B_15 Datasheet, PDF (5/22 Pages) THine Electronics, Inc. – 160MHz 51Bits LVDS Transmitter

THC63LVD823B_Rev.3.1_E
Pin Description (Continued)
Pin Name
Pin #
Type
Description
Output enable.
O/E
17
IN
H: Output enable,
L: Output disable (all outputs are Hi-Z).
H: Normal operation,
/PDWN
19
IN
L: Power down (all outputs are Hi-Z)
PRBS (Pseudo-Random Binary Sequence) generator is
active in order to evaluate eye patterns when
PRBS ^a
20
IN
MODE<1:0> = LL (Dual-in/Dual-out mode).
H: PRBS generator is enable.
L: Normal Operation
Reserved
21
IN
Must be tied to GND.
DDR function is active when
MODE<1:0> = HL (Single-in/Dual-out mode).
DDRN
13
IN
Open or H: DDR (Double Edge input) function disable.
L: DDR (Double Edge input) function enable.
N/C
22
Must be Open.
VCC
3, 55, 71, 87
Power Power Supply Pins for TTL inputs and digital circuitry.
GND
4, 18, 56,
72, 88
Ground Ground Pins for TTL inputs and digital circuitry.
LVCC
33, 45
Power Power Supply Pins for LVDS Outputs.
LGND
26, 38, 50
Ground Ground Pins for LVDS Outputs.
PVCC
24
Power Power Supply Pin for PLL circuitry.
PGND
23, 25
Ground Ground Pins for PLL circuitry.
a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of
2²³-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized
into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission
channel including PCB traces, connectors, and cables.
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.