THC63LVD823B_15 Datasheet, PDF (17/22 Pages) THine Electronics, Inc. – 160MHz 51Bits LVDS Transmitter

THC63LVD823B_Rev.3.1_E
LVDS Output Data Mapping (Continued)
•Table5. LVDS Output Data Mapping (Single-in/Dual-out, DDR On/Off, MODE<1:0>=HL, DDRN =Open/H/L)
LVDS
Mapping Mode (Input Pin Name)
LVDS
Mapping Mode (Input Pin Name)
Output Data
(1st Link)
Mode1
MAP=H
Mode2
MAP=L
Output Data
(2nd Link)
Mode1
MAP=H
Mode2
MAP=L
TA10
R12
R10
TA20
R12
R10
TA11
R13
R11
TA21
R13
R11
TA12
R14
R12
TA22
R14
R12
TA13
R15
R13
TA23
R15
R13
TA14
R16
R14
TA24
R16
R14
TA15
R17
R15
TA25
R17
R15
TA16
G12
G10
TA26
G12
G10
TB10
G13
G11
TB20
G13
G11
TB11
G14
G12
TB21
G14
G12
TB12
G15
G13
TB22
G15
G13
TB13
G16
G14
TB23
G16
G14
TB14
G17
G15
TB24
G17
G15
TB15
B12
B10
TB25
B12
B10
TB16
B13
B11
TB26
B13
B11
TC10
B14
B12
TC20
B14
B12
TC11
B15
B13
TC21
B15
B13
TC12
B16
B14
TC22
B16
B14
TC13
B17
B15
TC23
B17
B15
TC14
HSYNC
HSYNC
TC24
HSYNC
HSYNC
TC15
VSYNC
VSYNC
TC25
VSYNC
VSYNC
TC16
DE
DE
TC26
DE
DE
TD10
R10
R16
TD20
R10
R16
TD11
R11
R17
TD21
R11
R17
TD12
G10
G16
TD22
G10
G16
TD13
G11
G17
TD23
G11
G17
TD14
B10
B16
TD24
B10
B16
TD15
B11
B17
TD25
B11
B17
TD16
N/A
N/A
TD26
N/A
N/A
DE
GND
VCC
R1n,G1n,B1n
n=0 - 7
Hsync
Vsync
1st Pixel Data 2nd Pixel Data 1st Pixel Data 2nd Pixel Data
VCC
GND
Fig9. The decision rule of 1st Pixel data in Single IN/Dual Out DDR Off
(MODE<1:0>=HL, DDRN =Open or H)
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