THC63LVD824A Datasheet, PDF (4/15 Pages) THine Electronics, Inc. – Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA

THC63LVD824A _Rev1.20_E
Pin Description
Pin Name
RA1+, RA1-
RB1+, RB1-
RC1+, RC1-
RD1+, RD1-
RCLK1+, RCLK1-
RA2+, RA2-
RB2+, RB2-
RC2+, RC2-
RD2+, RD2-
RCLK2+, RCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKOUT
Pin #
78, 77
80, 79
83, 82
87, 86
85, 84
90, 89
92, 91
95, 94
99, 98
97, 96
52, 51, 50, 47,
46, 45, 44, 43
62, 61, 60, 59,
58, 55, 54, 53
72, 71, 68, 67,
66, 65, 64, 63
19, 18, 17, 14,
13, 12, 11, 10
29, 26, 25, 24,
23, 22, 21, 20
39, 38, 37, 36,
35, 32, 31, 30
75
74
73
40
DRVSEL
9
R/F
8
MODE1, MODE0
6, 5
/PDWN
VCC
GND
LVDS VCC
LVDS GND
4
15, 27, 33, 41,
48, 56, 69
3, 7, 16, 28, 34,
42, 49, 57, 70
81,93
76, 88, 100
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
Description
The 1st Link. The 1st pixel input data when Dual Link.
LVDS Clock Input for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Input for 2nd Link.
OUT
OUT The 1st Pixel Data Outputs.
OUT
OUT
OUT The 2nd Pixel Data Outputs.
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Power
Data Enable Output.
Vsync Output.
Hsync Output.
Clock Output.
Output Driverbility Select.
DRVSEL
clock
data
H
8mA
4mA
L
4mA
2mA
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
Pixel Data Mode.
MODE1 MODE0
L
L
L
H
other
Mode
Dual Link (Dual-in/Dual-out)
Single Link(Single-in/Dual-out)
Not Available
H: Normal operation,
L: Power down (all outputs are pulled to ground)
Power Supply Pins for TTL outputs and digital circuitry.
Ground
Power
Ground
Ground Pins for TTL outputs and digital circuitry.
Power Supply Pins for LVDS inputs.
Ground Pins for LVDS inputs.
Copyright©2014 THine Electronics, Inc.
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THine Electronics, Inc.