THC63LVD823 Datasheet, PDF (3/16 Pages) THine Electronics, Inc. – Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA

THC63LVD823 _Rev2.0
Pin Description
Pin Name
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
TCLK2+, TCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKIN
TEST1, TEST5
TEST3, TEST4
TEST2
/PDWN
6/8
OE
MODE1, MODE0
RS
Pin #
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
29, 30
60, 59, 58, 57,
54, 53, 52, 51
68, 67, 66, 65,
64, 63, 62, 61
78, 77, 76, 75,
74, 73, 70, 69
86, 85, 84, 83,
82, 81, 80, 79
96, 95, 94, 93,
92, 91, 90, 89
6, 5, 2, 1, 100,
99, 98, 97
9
8
7
10
13, 22
20, 21
14
19
18
17
15, 16
12
Type
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
Description
The 1st Link. The 1st pixel output data when Dual Link.
LVDS Clock Out for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Out for 2nd Link.
IN
IN
The 1st Pixel Data Inputs.
IN
IN
IN
The 2nd Pixel Data Inputs.
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
Data Enable Input.
Vsync Input.
Hsync Input.
Clock Input.
Test Pins.
Test Pins, must be L for normal operation.
Test Pins, must be H for normal operation.
H: Normal operation,
L: Power down (all outputs are Hi-Z)
6bit/8bit color select.
H: 6bit (TDx+/- are GND), L: 8bit.
Output enable.
H: Output enable, L: Output disable (all outputs are Hi-Z)
Pixel Data Mode.
MODE1 MODE0
L
L
L
H
H
H
Mode
Dual Link (Dual-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
LVDS swing range select.
H: Normal range, L: Reduced range.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.