THC63LVD1023B Datasheet, PDF (3/26 Pages) THine Electronics, Inc. – 160MHz 67Bits LVDS Transmitter

THC63LVD1023B _Rev.3.0_E
Pin Description
Pin Name
ASYNC=L ASYNC=H
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TE1+, TE1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
TE2+, TE2-
Pin #
70, 71
68, 69
64, 65
58, 59
56, 57
62, 63
52, 53
50, 51
46, 47
40, 41
38, 39
TCLK2+, TCLK2-
44, 45
R19 ~ R10
TB12~TB10,
TA16~TA10
G19 ~ G10
TC15~TC10,
TB16~TB13
B19 ~ B10
TE11~TE10,
TD16~TD10,
TC16
R29 ~ R20
G29 ~ G20
B29 ~ B20
TA24~TA20,
TE16~TE12
TC20,
TB26~TB20,
TA26~TA25
TD23~TD20,
TC26~TC21
87 - 84,
81 - 76
99 - 95,
92 - 88
112 -110,
108 -106,
103 - 100
124 - 115
136 - 127
6, 5, 2, 1,
144 - 139
Type
Description
The 1st Link.
The 1st pixel output data when Dual-Link.
LVDS Clock Out for 1st and 2nd Link.
The 2nd Link.
These pins are disabled when Single Link.
LVDS
OUT
See following table.
ASYNC MODE0 MODE1
H
x
x
H
x
x
L
L
x
L
H
L
L
H
H
L
H
H
MODE2
L
H
x
x
L
H
Description
Case1
Case2
Case3
Case4
Case4
Case3
Case1: LVDS Clock out for 2nd link.
Case2: LVDS Clock out for 1st link.
Case3: Additional LVDS Clock out.
Identical to TCLK1+/-
Case4: Not available (High-Impedance)
ASYNC=L
The 1st Pixel Data Inputs.
IN
ASYNC=H
Data Inputs.
ASYNC=L
The 2nd Pixel Data Inputs.
IN
ASYNC=H
Data Inputs.
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THine Electronics, Inc.