DS1302 Datasheet, PDF (11/14 Pages) Dallas Semiconductor – Trickle Charge Timekeeping Chip

TIMING DIAGRAM: READ DATA TRANSFER Figure 5
DS1302
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at V_CC=5V and 0.4 mA at V_CC=2.0V,
V_OH=V_CC for capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at V_CC=5V and 1.5 mA at V_CC=2.0V,
V_OL=GND for capacitive loads.
4. I_CC1T and I_CC2T are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator
enabled).
5. I_CC1A and I_CC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at V_CC=5V;
SCLK=500 kHz, V_CC=2.0V and clock halt flag=0 (oscillator enabled).
6. RST , SCLK, and I/O all have 40 kΩ pull–down resistors to ground.
7. Measured at V_IH=2.0V or V_IL=0.8V and 10 ns maximum rise and fall time.
8. Measured at V_OH=2.4V or V_OL=0.4V.
9. Load capacitance = 50 pF.
10. I_CC1S and I_CC2S are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic
one (oscillator disabled).
11. V_CC=V_CC2, when V_CC2>V_CC1 +0.2V; V_CC=V_CC1, when V_CC1>V_CC2.
12. V_CC2=0V.
13. V_CC1=0V.
14. Typical values are at 25°C.
11 of 14