71M6515H Datasheet, PDF (15/57 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
If the 71M6515H is interfacing to an external DSP (typically, but not necessarily through the SSI interface), the host may turn
off post-processing by setting the CE_ONLY bit in the CONFIG word. This will permit setting SUM_CYCLES below its
recommended lower limit of 24. SUM_CYCLES may then be reduced to 1, creating an accumulation interval of only 42 samples.
The outputs available in CE only mode are limited to temperature, frequency, voltage phases, input signal zero crossings, plus
WSUM and VARSUM for each phase and VSQSUM, ISQSUM, and ISQFRACT for each phase.
Pulse Generators
The chip contains four pulse generators connected to the pins PULSEW, PULSER, PULSE3, and PULSE4 that create low jitter
pulses from 32-bit data. The peak time jitter for PULSEW and PULSER is the 397µs MUX frame period, and is independent of
the rate of the generator or the length of time the generator is monitored. Thus, if the pulse generator is monitored for 1
second, the peak jitter is 400PPM. After 10 seconds, the peak jitter is 40PPM.
PULSE3 and PULSE4 are updated at a slower rate and have four times higher jitter, i.e. 160PPM after 10 seconds.
The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply
output at its maximum rate without exhibiting any roll-over characteristics.
Pulse generator inputs may be from three sources:
• Internal (directly from the CE), PULSEW and PULSER only
• External (controlled by the host writing to registers APULSEW, APULSER, APULSE3, APULSE4)
• Post-processed values
The source is selected individually for each pulse output with the PULSEW_SRC, PULSER_SRC, PULSE3_SRC, and PULSE4_SRC
registers. Figure 8 shows internal pulse generation for the PULSEW output selected by writing the value 35 into the
PULSEW_SRC register.
35: WSUM
CE
35
PULSEW_SRC
0: WSUM
1: WASUM
2: WBSUM
3: WCSUM
4: VARSUM
PULSEW
OUTPUT
34: VAR2SUM_E
36: APULSEW
HOST
Figure 8: Internal Pulse Generation Selected in the PULSEW_SRC Register
Internal data is pulsed out during the accumulation interval immediately following its accumulation interval. Post-processed
values are pulsed out one accumulation interval after that.
Page: 15 of 57
© 2005-2008 TERIDIAN Semiconductor Corporation
V1.4