DG183 Datasheet, PDF (8/8 Pages) TEMIC Semiconductors – High-Speed Drivers with Dual DPST JFET Switches

DG183/184/185
Test Circuits
Feedthrough due to charge injection may result in spikes at the leading and trailing edge of the output waveform.
+5 V
+15 V
V_L
V_S1
S₁
V_S2
S₂
IN
GND
V+
D₁
D₂
V–
–15 V
t_ON: V_S = 3 V
t_OFF: V_S = –3 V
V_O2
3V
Logic
Input
V_O1
0V
3V
R_{L2 CL2}
R_{L1 CL1}
0V
Switch
Output
50%
90%
t_ON
C_L (includes fixture and stray capacitance)
R_L
V_OUT + V_S x _{RL ) rDS(on)}
–3 V
Figure 2. Switching Time
t_r <10 ns
t_f <10 ns
t_OFF
0V
90%
Application Hints^a
Switch
DG183
DG184
DG185
V+
Positive Supply
Voltage
(V)
15^b
10
12
15^b
10
12
V–
Negative
Supply Voltage
(V)
–15
–20
–12
–15
–20
–12
V_L
Logic
Supply Voltage
(V)
5
5
5
5
5
5
V_R
Reference
Supply Voltage
(V)
GND
GND
GND
GND
GND
GND
V_IN
Logic Input Voltage
V_INH(min)/V_INL(max)
(V)
2.0/0.8
2.0/0.8
2.0/0.8
2.0/0.8
2.0/0.8
2.0/0.8
V_S
Analog Voltage
Range
(V)
–7.5 to 15
–12.5 to 10
–4.5 to 12
–10 to 15
–15 to 10
–7 to 12
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Electrical Parameter Chart based on V+ = 15 V, V_L = 5 V, V_R = GND.
8
Siliconix
S-52895—Rev. D, 16-Jun-97