U2782B Datasheet, PDF (7/10 Pages) TEMIC Semiconductors – 1100 MHz Twin PLL

Timing Diagram Serial Bus
Data
Clock
Enable
t_SEC t_CH t_CL
Internal
Loadpulse
U2782B
t_SDC
t_HDC
t_EL
t_HCE t_HEC
96 11828
Clock High Time
t_CH
>750
ns
Clock Low Time
t_CL
>350
ns
Clock Period
t_PER
>1100
ns
Set up Time Clock Data to Clock
t_SDC
>100
ns
Hold Time Data to Clock
t_HDC
>400
ns
Hold Time Clock to Enable
t_HCE
>400
ns
Hold Time Enable to Clock
t_HEC
>400
ns
Enable Low Time
t_EL
>200
ns
Set up Time Enable to Clock
t_SEC
>4000
ns
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3000
96 11679
5I=1
30000
R19/ W
300000
Figure 3. Charge pump characteristics
1000
100
Guaranteed Area
10
1
0
96 11680
200 400 600 800 1000 1200
Frequency/ MHz
Figure 4. Input sensitivity of PLL1 and PLL2
TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97
7 (10)