U2782B Datasheet, PDF (4/10 Pages) TEMIC Semiconductors – 1100 MHz Twin PLL

U2782B
Serial Bus Programming
Reference and programmable counters can be
programmed by the 3-wire-bus (Clock, Data and Enable).
After setting enable signal to high condition, the data sta-
tus is transfered but by but on the rising edge of the clock
signal into the shift register, starting with the MSB-bit.
After the Enable signal returns to low condition the
programmed information is loaded according to the
addressbits (last three bits) into the addressed latch.
Additional leading bits are ignored and there is no check
made how many clock pulses arrived during enable high
condition. In powerdown mode the 3-wire-bus remains
active and the IC can be programmed.
Data is entered with the most significant bit first. The
leading bits deliver the divider or control information.
The trailing three bits are the address field. There are six
different addresses used. The trailing address bits are
decoded upon the falling edge of the Enable signal. The
internal Loadpulse is beginning with the falling edge of
the Enable signal and ending with falling edge of the
Clock signal. Therefore a minimum holdtime clock-
enable t_HCE is required.
Bit Allocation
MSB
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
1 2 3 4 5 6 7 8 9 10 11 12 13
data bits
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
PLL1
M10 ^{M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S5 S4}
PLL1
R11 ^{R10 R9 R8 R7 R6 R5 R4}
PLL2
M10 ^{M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S5 S4}
PLL2
R11 ^{R10 R9 R8 R7 R6 R5 R4}
RF/ Test 5IP TRI TRI PS2 PS1 H2P H1P LP LPA P4
2
21
B
LSB
Bit Bit Bit Bit Bit Bit Bit
14 15 16 17 18 19 20
address bits
D3 D2 D1 D0 A2 A1 A0
PLL1
S3 S2 S1 _S0 0 0 1
PL1
R3 R2 R1 _R0 0 1 0
PLL2
S3 S2 S1 _S0 0 1 1
PLL2
R3 R2 R1 _R0 1 0 0
P3 P2 P1 P0 1 0 1
SP SP SP
D 5I D 2 D 1 1 1 0
Scaling Factors
S0 ... S5:
These bits are setting the swallow counter S_S.
T_S = S0*2⁰ + S1*2¹ + ... + S4*2⁴ + S5*2⁵
allowed scalling factors for S_S: 0 ... 63, T_S < T_M
M0 ... M10: These bits are setting the main counter S_M.
T_M = M0*2⁰ + M1*2¹ + ... + M9*2⁹ + M10*2¹⁰
allowed scalling factors for S_M: 5 ... 2047
S_PGD: Total scalling factor of the programmable counter:
S_PGD = (64*S_M) + S_S Condition: S_S < S_M
R0 ... R11:
These bits are setting the reference counter S_R.
S_R = R0*2⁰ + ... + R10*2¹⁰ + R11*2¹¹
allowed scalling factors for S_R: 5 ... 4096
S_RFD: Total scalling factor of the reference counter:
RF/2 = 1: S_RFD = 2 * S_R
RF/2 = 0: S_RFD = S_R
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TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97