U2102B Datasheet, PDF(6/16 Page) TEMIC Semiconductors

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

U2102B Datasheet, PDF (6/16 Pages) TEMIC Semiconductors – Multifunction Timer

◁

U2102B

Voltage Monitoring

Reverse Phase Control, Pins 2, 3, 4

While the operating voltage is being built up or reduced,

uncontrolled conditions or output pulses of insufficient

amplitude are being suppressed by the internal moni-

toring circuit. All latches in the circuit, the divider and the

control logic are reset. When the supply voltage is

applied, the enable threshold (clamp voltage) of approxi-

mately 16 V must be reached so that the circuit is enabled.

The circuit is reset at approximately 11 V if the supply

voltage breaks down. A further threshold is activated in

reverse phase control mode. If the supply voltage breaks

down here after enabling of the circuit, the output stage

is switched off at approximately 12.5 V, while the other

parts of the circuit are not affected. The output stage can

then be switched on again only in the following half-

wave. As a result, the residual phase angle remains just

large enough, (e.g., in two-wire systems), so that the

circuit can still be properly supplied with power. In all

operating modes, a single operating cycle is started after

the supply voltage is applied, independently of the trigger

inputs, in order to immediately demonstrate the overall

function.

Chip Temperature Monitoring

The circuit possesses an integrated chip temperature

monitoring circuit which disables the output stage when

a temperature of approximately 140Â°C is reached. The

circuit is enabled again only after cooling down and addi-

tionally switched âoff and onâ of the operating voltage.

Vmains

In the case of normal phase controls, e.g., with a triac, the

load current is switched ON only at a certain phase angle

after the zero crossing of the mains voltage. In the

following zero crossing of the current, the triac gets extin-

guished (switched-off) automatically. Reverse phase

control differs from this in that the load current is always

switched-on by a semiconductor switch (e.g., IBGT) at

the zero crossing of the mains voltage and then switched

back off again after a certain phase angle a. This has the

advantage that the load current always rises with the

mains voltage in a defined manner and thus keeps the

required interference suppression to a minimum.

The charging current for the capacitor C3 at Pin 2 is set

with the resistor R3 at Pin 3. When the synchronization

circuit recognizes a zero crossing, an increased charging

[ current I2 4 I3 is enabled which then charges C3 up

[to 0.45 V. The output stage is switched-on at this value

and the charging current for C3 is reduced to I2 = I3. Since

the actual zero crossing of the supply voltage occurs later

than recognized by the circuit, the load current starts to

flow quite close to the exact zero crossing of the supply

voltage. While the output stage is switched-on C3 is

charged until the control voltage, set externally at Pin 4,

is reached. When this condition is reached, the output

[ stage is switched off and C3 is charged again with the

increased current (I2 = 4 I3) to V2 5.5 V. The

charging current is switched off at this point and C3 is

discharged internally. The whole process then starts again

when the circuit recognizes another zero crossing (see

figure 6).

1.1 VRef

0.09 VRef

V14

94 8290 e

6 (16)

Figure 6. Signal characteristics of reverse phase control

TELEFUNKEN Semiconductors

Rev. A1, 30-May-96

▷