U2752M Datasheet, PDF (4/6 Pages) TEMIC Semiconductors – Digital I/Q-Generator Chip for DAB

U2752M
Input Interface Description
RESET
CLOCK
Internal RI
selection signal
DATA_IN
RI
R
I
tsu_din
Figure 3. Input interface signals (tsu_din ≥ 10 ns)
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For verification purposes, it can be helpful to know how
the U2752M selects the input samples for real and imagi-
nary data processing.
The U2752M generates an internal real and imaginary
selection signal, which depends on the first recognized
rising CLOCK edge as shown in figure 3. Due to this
selection signal, the data input DATA_IN will be used for
the real or imaginary process path of the IC. The setup
time of DATA_IN tsu_din must be ≥ 10 ns.
Results
The phase deviation from 90° of the I- and Q- parts over
the normalized frequency is shown in figure 4.
The DAB-relevant frequency range is from 1/8 to 7/8 on
the normalized frequency axis.
For the DAB frequency range, the maximum phase mis-
match is 1.6° and the amplitude mismatch is 0 dB.
100
80
max. phase mismatch = 1.6 deg
60
max. amplitude mismatch = 0 dB
40
20
0
–20
–40
–60
–80
–100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
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Normalized frequency
Figure 4. Phase deviation of the I- and Q–parts
4 (6)
Rev. A1, 29-Jun-98
Preliminary Information