U2752M Datasheet, PDF (2/6 Pages) TEMIC Semiconductors – Digital I/Q-Generator Chip for DAB

U2752M
Pin Description
Pin
Signal
Description
PAD Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
MIX_OFF
Low: I/Q in baseband representation, High. I/Q in IF representation
BUFINCDN
2
RESET
Reset signal, high active
BUFINCDN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₃
VSS
Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₄
DATA_IN0
Data input (LSB)
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₅
DATA_IN1
Data input
BUFINMOS
6
DATA_IN2
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₇
DATA_IN3
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₈
DATA_IN4
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₉
DATA_IN5
Data input
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 10
DATA_IN6
Data input
BUFINMOS
11
DATA_IN7
Data input (MSB)
BUFINMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₂
VSS
Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₃
CLOCK
System clock 4.096 MHz
BUFTGMOS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 14
DATA_RI
Internal data_ri signal
BU2OUT
15
VDD
Power supply
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₆
IQDATA7
Data_output, I and Q multiplex (MSB)
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₇
IQDATA6
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₈
IQDATA5
Data_output, I and Q multiplex
BU2OUT
19
IQDATA4
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₂₀
IQDATA3
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₂₁
IQDATA2
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₂₂
IQDATA1
Data_output, I and Q multiplex
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 23
IQDATA0
Data_output, I and Q multiplex (LSB)
BU2OUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ²⁴
VDD
Power supply
MIX_OFF 1
RESET 2
24 VDD
23 ^IQDATA0
VSS 3
22 ^IQDATA1
DATA_IN0 ⁴
DATA_IN1 5
21 IQDATA2
20 ^IQDATA3
DATA_IN2 ⁶
19 IQDATA4
DATA_IN3 ⁷
18 IQDATA5
DATA_IN4 8
17 ^IQDATA6
DATA_IN5 ⁹
16 IQDATA7
DATA_IN6 10
15 VDD
DATA_IN7 ¹¹
14 DATA_RI
VSS 12
13 CLOCK
96 12266
Figure 2. Pinning
Functional Description
The U2752M generates the in-phase and quadrature
components of the DAB input signal with a quadrature
matching of 0 dB in magnitude and a maximum value of
1.6° in phase. The clock of the device is 4.096 MHz.
The data format of the input signal DATA_IN is 8 bits,
sampled with 4.096 MHz in 2’s complement represen-
tation. Its center frequency is 3.072 MHz with a
bandwidth of 1536 MHz. The U2752M uses decimation
and common filter techniques to generate the quadrature
components.
The output interface consists of the split signal IQDATA
with a data format of 8 bits, 4.096 MHz in 2’s comple-
ment representation. The in-phase (I) and quadrature (Q)
components are represented in time division multiplex
format with a selection signal DATA_RI of 4.096 MHz.
The output representation in baseband or 1.024-MHz
center frequency is selected by the MIX_OFF signal. For
utilization together with TEMIC’s U2752M device, the
baseband representation (MIX_OFF = ‘0’) must be
selected.
2 (6)
Rev. A1, 29-Jun-98
Preliminary Information