U2730B-B Datasheet, PDF (3/12 Pages) TEMIC Semiconductors – L-Band Down-Converter for DAB Receivers

U2730B-B
Functional Description
The U2730B-B is an L-band down-converter circuit
covering a gain-controlled amplifier, a gain-controlled
mixer, an output buffer, a gain-control circuitry, an
L-band oscillator and a frequency synthesizer block.
Designed for applications in an DAB receiver, the
purpose of this circuit is to down-convert incoming
L-band signals in the frequency range of 1452 MHz to
1492 MHz to an IF frequency in the range of about
190 MHz to 230 MHz which can be handled by a
subsequent DAB tuner. A block diagram of this circuit is
shown in figure 1.
Gain-Controlled Amplifier
RF signals applied to the input Pin RF are amplified by a
gain-controlled amplifier. Although the complementary
Pin NRF is internally blocked, it is recommended to
block this pin additionally by an external capacitor. The
gain-control voltage is generated by an internal gain-
control circuitry. The output signal of this amplifier is fed
to a gain-controlled mixer.
Gain-Controlled Mixer and Output Buffer
The purpose of this mixer is to down-convert the L-band
signal in the frequency range of 1452 MHz to 1492 MHz
to an IF frequency in the range of about 190 MHz to
230 MHz. Like the amplifier, the gain of the mixer is
controlled by the gain-control circuitry. The IF signal is
buffered and filtered by a one-pole lowpass filter at a
3-dB frequency of about 500 MHz and then it is fed to the
single-ended output Pin IF.
Gain-Control Circuitry
The purpose of the gain-control circuitry is to measure the
signal power, to compare it with a certain power level and
to generate control voltages for the gain-controlled
amplifier and mixer. An equivalent circuit of this
functional block is shown in figure 4.
In order to meet this functionality, the output signal of the
buffer amplifier is weakly bandpass filtered (transition
range about 60 MHz to 550 MHz), rectified, lowpass
filtered and fed to a comparator whose threshold can be
defined by an external resistor, R_TH, at Pin TH. By
varying the value of this resistor, a power threshold of
about –35 dBm to –25 dBm can be selected. In order to
achieve a good intermodulation ratio, it is recommended
to keep the power threshold below –30 dBm. An
appropriate application is shown in figure 3. Depending
on the selection made by the comparator, a charge pump
charges or discharges a capacitor which is applied to the
Pin AGC. By varying this capacitor, different time
constants of the AGC loop can be realized. The voltage
arising at the Pin AGC is used to control the gain setting
of the gain-controlled amplifier and mixer. By applying
an external voltage to the Pin AGC the internal AGC loop
can be overdriven.
Voltage-Controlled Oscillator
A voltage-controlled oscillator supplies an LO signal to
the mixer. An equivalent circuit of this oscillator is shown
in figure 5. In the application circuits figures 3 and 5, a
ceramic coaxial resonator is applied to the oscillator’s
Pins TANK and REF. It should be noted that the Pin REF
has to be blocked carefully. Figure 6 shows a different
application where the oscillator is overdriven by an
external oscillator. In any case, a DC path at a low
impedance must be established between the Pins TANK
and REF. The output signal of the oscillator is fed to the
LO divider block of the frequency synthesizer unit which
locks the VCO’s frequency on the frequency of a
reference signal applied to the Pins REF and NREF.
Figure 7 shows the typical phase-noise performance of
the oscillator in locked state.
Overall Properties of the Signal Path
The overall gain of this circuit amounts 21 dB, the gain-
control range is about 32 dB.
Frequency Synthesizer
The frequency synthesizer block consists of an input
buffer for a reference signal, a reference divider, an LO
divider to divide the frequency of the internal oscillator,
a tristate phase detector, a lock detector, a programmable
charge pump, a loop filter amplifier, a control interface
and a test interface. The control interface is accessed by
two control pins, Pins C and S. The test interface provides
test signals which represent output signals of the
reference and the LO divider.
The purpose of this unit is to lock the frequency, f_VCO, of
the internal VCO on the frequency, f_ref, of the reference
signal applied to the input Pins REF and NREF by a
phase-locked loop according to the following equation:
f_VCO = SF f_ref / SF_ref
where:
SF
SF_ref
= 2464
= scaling factor of reference divider
according to the following table
Voltage at Pin S (Pin 27)
Ground
V_CC / 2
Open
V_CC
V_CC-supply voltage
SF_ref
35
32
48
36
Rev. A1, 22-Jul-98
3 (12)
Preliminary Information