U6084B Datasheet, PDF (2/8 Pages) ATMEL Corporation – PWM Power Control with Automatic Duty-cycle Reduction

U6084B
Pin Description
GND 1
En / Dis ₂
V_{I 3}
Reduct 4
Attenuation 5
Osc ₆
NC 7
NC 8
16 V_S
15 NC
14 Output
13 2 V_S
12 Sense
11 ^Delay
10 ^NC
9 Latch
95 9754
Pin Symbol
Function
1
GND IC ground
2 En / Dis Enable/disable
3
V_I Control input (duty cycle)
4 Reduct Duty cycle reduction
5
NC Attenuation
6
Osc Oscillator
7
NC Not connected
8
NC Not connected
9
Latch Status short circuit latch
10
NC Not connected
11 Delay Short circuit protection delay
12 Sense Current sensing
13
2V_S Voltage doubler
14 Output Output
15
NC Not connected
16
V_S Supply voltage V_S
Functional Description
Pin1, GND
Ground-Wire Breakage
To protect the FET in the case of ground-wire breakage,
a 820 kW resistor between gate and source it is recom-
mended to provide proper switch-off conditions.
Pin 2, Enable/Disable
The dimmer can be switched on or off with pin 2 indepen-
dently of the set duty cycle.
V₂
Approx. >0.7 V or open
Function
Disable
< 0.7 V or connected to Pin 1 Enable
Pin 3, Control Input
The pulse width is controlled by means of an external po-
tentiometer (47 kW). The characteristic (angle of
rotation/duty cycle) is linear. The duty cycle can be varied
from 0 to 100%. It is possible to further restrict the duty
cycle with the resistors R₁ and R₂ (see figure 2).
x ^{Pin 3 is protected against short-circuit to VBatt and ground}
GND (V_Batt 16.5 V).
Pin 4, Duty Cycle Reduction
 ^{With Pin 4 connected according to figure 2, the set duty}
cycle is reduced as from V_Batt 12.5 V. This causes a
power reduction in the FET and in the lamps. In addition,
the brightness of the lamps is largely independent of the
supply voltage range, V_Batt = 12.5 to 16 V.
Output Slope Control
The rise and fall time (t_r, t_f) of the lamp voltage can be
limited to reduce radio interference. This is done with an
integrator which controls a power MOSFET as source fol-
lower. The slope time is controlled by an external
capacitor C4 and the oscillator current (see figure 2).
Calculation:
+ + t_f
t_r V_Batt
C₄
I_osc
With V_Batt = 12 V, C₄ = 470 pF and I_osc = 40 m A,we thus
obtain a controlled slope of
+ + + ^{470 pF}
t_f t_r 12 V _{40 mA}
141 ms
Pin 5, Attenuation
Capacitor C₄ connected to Pin 5 damps oscillation
tendencies.
Pin 6, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C₂. It is
2 (8)
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97