U2893B Datasheet, PDF (12/14 Pages) TEMIC Semiconductors – Modulation PLL for GSM, DCS and PCS Systems

U2893B
Measurements
Modulation-Loop Settling Time
As valid for all PLL loops the settling time depends on
several factors. The following figure is an extraction from
measurements performed in an arrangement like the ap-
plication circuit. It shows that a loop settling time of a few
ms can be achieved.
CPC: 1 kΩ to GND
Modulation Spectrum & Phase Error
The figure of the TX spectrum and the phase error dis-
tribution, respectively, shows the suitability of the
modulation-loop concept for GSM.
Vertical: VRef. level = 28.6 dBm, 10 dBm/Div
Horizontal: Center = 900 MHz, VBW, RBW = 30 kHz,
400 kHz/Div
CPC ‘open’
Vertical: VCO tuning voltage 1 V/Div
Horizontal: Time 1 ms/Div
Figure 17.
Figure 18.
Figure 19.
12 (14)
TELEFUNKEN Semiconductors
Preliminary Information
Rev. A1, 29-Jan-76