U2896B Datasheet, PDF (11/13 Pages) TEMIC Semiconductors – Modulation PLL for GSM, DCS and PCS Systems

U2896B
Application Circuit for DCS1800 (1710 – 1785 MHz)
R1
1
Baseband _R2
R3
C1
2
36
C12
35
2nd LO
–10dBm
C2
3
34
C3
4
33
R9
R8 _R10
Baseband
3V
5
C4
3V
6
7
8
3V, 5V
Tuning voltage
R4
C7
9
10
C5
11
C6
12
C8 ^L1
R5
R6
C9
L2
C10
13
14
15
C11
16
R7
3V
17
U2896B
32
31
30
C14
29
C15
28
27
26
C17
25
C18
24
23
C19
22
C20
21
20 n.c.
3V
C13
VCO
880 to 915MHz
1710 to 1785MHz
–20dBm
3V
C16
1st LO
–15dBm
3V
L3
C29
n.c. 18
19 ^n.c.
14904
Measurements
Modulation-Loop Settling Time
Figure 14. Application circuit
Modulation Spectrum & Phase Error
CPC: 1 kΩ to GND
As valid for all PLL loops the settling time depends on
several factors. The following figure is an extraction from
measurements performed in an arrangement like the
application circuit. It shows that a loop settling time of a
few ms can be achieved.
CPC ‘open’
Vertical: VCO tuning voltage 1 V/Div
Horizontal: Time 1 ms/Div
Rev. A1, 18-Sep-98
Preliminary Information
11 (13)