U2894B Datasheet, PDF (11/16 Pages) TEMIC Semiconductors – Modulation PLL for GSM, DCS and PCS Systems

Application Circuit for DCS1800 (1710 – 1785 MHz)
U2894B
Baseband processor
Attention!
Differential source impedance
seen by the I/NI, Q/NQ inputs
should not exceed 1000 Ohms
2.7 to 3.5 V
r_diff
200 Ω ^{15 nH}
2x
15 pF
f_LO (–10 dBm)
1310–1385 MHz
12
3 28 27
12 nH 12 nH
5
4.7 pF ₆
2 pF
24 nH
820 Ω
2 pF
16
4.7 pF ₁₇
13
f_Ref
V_rms = 55 mV _{50 Ω}
14
(400 MHz)
90°
+
I/Q modulator
N1
divider
R1
divider
MUX
12 19 25 20
Voltage
reference
Mixer
Charge
PFD
pump
36 kΩ
15 _Mode
control
4 18 24
11
10
22
50 Ω 390 Ω
6 dB ^{to PA}
23
attn. _{f_TX}
(1710–
2.7 _{VCO 1785 MHz)}
8 ^{to 3.5 V}
MQE5A1–1747
9
68 pF
3.3 nF
390 Ω
7
21
2.7 to 3.5 V
26
14570
Figure 16. Application circuit (power-up and charge-pump control is not shown)
Measurements
Modulation-Loop Settling Time
CPC: 1 kΩ to GND
As valid for all PLL loops the settling time depends on
several factors. The following figure is an extraction from
measurements performed in an arrangement like the ap-
plication circuit. It shows that a loop settling time of a few
ms can be achieved.
CPC ‘open’
Vertical: VCO tuning voltage 1 V/Div
Horizontal: Time 1 ms/Div
Figure 17.
Rev. A4, 30-Sep-98
11 (16)