TC1072 Datasheet, PDF (5/12 Pages) TelCom Semiconductor, Inc – 50mA CMOS LDO WITH SHUTDOWN, ERROR OUTPUT AND VREF BYPASS

50mA CMOS LDO WITH SHUTDOWN,
ERROR OUTPUT AND V_REF BYPASS
PRELIMINARY INFORMATION
TC1072
The following equation is used to calculate worst case
actual power dissipation:
P_{D ≈} (V_{INMAX –} V_{OUTMIN)ILOADMAX}
Where:
P_D = Worst case actual power dissipation
V_INMAX = Maximum voltage on V_IN
V_OUTMIN = Minimum regulator output voltage
I_LOADMAX = Maximum output (load) current
Equation 1.
The maximum allowable power dissipation (Equation 2)
is a function of the maximum ambient temperature (T_AMAX),
the maximum allowable die temperature (125°C) and the
thermal resistance from junction-to-air (θ_JA). SOT-23A-6
packag has a θ_JA of approximately 220°C/Watt when
mounted on a single layer FR4 dielectric copper clad PC
board.
P_{D MAX =} (T_JMAX – T_AMAX)
θ_JA
Where all terms are previously defined.
Equation 2.
Equation 1 can be used in conjunction with Equation 2
to ensure regulator thermal operation is within limits. For
example:
Given:
V_INMAX = 3.0V ±10%
V_OUTMIN = 2.7V ±0.5V
I_LOAD = 40mA
T_AMAX = 55°C
Find: 1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P_{D ≈} (V_{INMAX –} V_{OUTMIN)ILOADMAX}
= [(3.0 x 1.05) – (2.7 x .995)]40 x 10^–3
= 18.5mW
Maximum allowable power dissipation:
P_DMAX = (T_JMAX – T_AMAX)
θ_JA
= (125 – 55)
220
= 318mW
In this example, the TC1072 dissipates a maximum of
only 60mW; far below the allowable limit of 318mW. In a
similar manner, Equation 1 and Equation 2 can be used to
calculate maximum current and/or input voltage limits.
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower θ_JA and therefore in-
crease the maximum allowable power dissipation limit.
TC1072-01 6/16/97
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