TC1232 Datasheet, PDF (4/6 Pages) TelCom Semiconductor, Inc – MICROPROCESSOR MONITOR

MICROPROCESSOR MONITOR
TC1232
DETAILED DESCRIPTION
Power Monitor
The TC1232 detects out-of-tolerance power supply
conditions and warns a processor-based system of an
impending power failure. When V_CC is detected as below the
preset level defined by TOL, the V_CC comparator outputs the
signals RST and RST. If TOL is connected to ground, the
RST and RST signals become active as V_CC falls below 4.75
volts. If TOL is connected to V_CC, the RST and RST become
active as V_CC falls below 4.5 volts. Because the processing
is stopped at the last possible moment of valid V_CC, the RST
and RST are excellent control signals for a µP. The reset
outputs will remain in their active states until V_CC has been
continuously in-tolerance for a minimum of 250msec allow-
ing the power supply and µP to stabilize before RST is
released.
Push-button Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once
PB RST has been low for a time t_PBD, the push-button delay
time, the reset outputs go active. The reset outputs remain
in their active states for a minimum of 250msec after PB RST
rises above V_IH (Figure 3).
A mechanical push-button or active logic signal can
drive the PB RST input. The debounced input ignores input
pulses less than 1msec and is guaranteed to recognize
pulses of 20msec or greater. No external pull-up resistor is
required because the PB RST input has an internal pull-up
to V_CC of approximately 100µA.
Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is deter-
mined by the TD inputs to be 150msec with TD connected
to ground, 600msec with TD floating, or 1200msec with TD
connected to V_CC, typical. The watchdog timer starts timing
out from the set time period as soon as RST and RST are
inactive. If a high-to-low transition occurs on the ST input pin
prior to time-out, the watchdog timer is reset and begins to
time-out again. If the watchdog timer is allowed to time-out,
then the RST and RST signals are driven to the active state
for 250msec minimum (Figure 2).
The software routine that strobes ST is critical. The code
must be in a section of software that is executed frequently
enough so the time between toggles is less than the watch-
dog time-out period. One common technique controls the µP
I/O line from two sections of the program. The software
might set the I/O line high while operating in the foreground
5-22
mode and set it low while in the background or interrupt
mode. If both modes do not execute correctly, the watchdog
timer issues reset pulses.
Supply Monitor Noise Sensitivity
The TC1232 is optimized for fast response to negative-
going changes in V_DD. Systems with an inordinate amount
of electrical noise on V_DD (such as systems using relays),
may require a 0.01µF or 0.1µF bypass capacitor to reduce
detection sensitivity. This capacitor should be installed as
close to the TC1232 as possible to keep the capacitor lead
length short.
+5V
V_CC
PB RST
TD
ST
RST
TC1232
GND TOL
I/O
MICROPROCESSOR
RESET
Figure 1. Push-button Reset
+5V
10KΩ
3 -TERMINAL
REGULATOR
+5V
V_CC
RST
0.1
µF
TC1232
RESET
MICROPROCESSOR
ST
I/O
TD TOL GND
Figure 2. Watchdog Timer
TELCOM SEMICONDUCTOR, INC.