TCM809 Datasheet, PDF (3/4 Pages) TelCom Semiconductor, Inc – 3-PIN UP RESET MONITORS

3-PIN µP RESET MONITORS
1 ^{PRELIMINARY INFORMATION}
TCM809
TCM810
APPLICATIONS INFORMATION
V_CC Transient Rejection
The TCM809/810 provides accurate V_CC monitoring
and reset timing during power-up, power-down, and brown-
out/sag conditions, and rejects negative-going transients
(glitches) on the power supply line. Figure 1 shows the
maximum transient duration vs. maximum negative excur-
sion (overdrive) for glitch rejection. Any combination of
duration and overdrive which lies under the curve will not
generate a reset signal. Combinations above the curve are
detected as a brownout or power-down. Transient immunity
can be improved by adding a capacitor in close proximity to
the V_CC pin of the TCM809/810.
V_CC
V_TH
Overdrive
valid to V_CC = 0V, a pull-down resistor must be connected
2 ^{from RESET to ground to discharge stray capacitances and}
hold the output low (Figure 2). This resistor value, though
not critical, should be chosen such that it does not apprecia-
bly load RESET under normal operation (100kΩ will be
suitable for most applications). Similarly, a pull-up resistor to
V_CC is required for the TCM810 to ensure a valid high
RESET for V_CC below 1.0V.
V_CC
3
V_CC
TCM809
RESET
R1
4
GND
100k
Duration
400
T_A = +25°C
320
240
160
TCM8xxLM
80
TCM8xxR/S/T
0
1
10
100
1000
RESET COMPARATOR OVERDRIVE,
(VTH - VCC (mV)
Figure 1. Maximum Transient Duration vs.
Overdrive for Glitch Rejection at 25°C
RESET Signal Integrity During Power-Down
The TCM809 RESET output is valid to V_CC = 1.0V.
Below this voltage the output becomes an "open circuit" and
does not sink current. This means CMOS logic inputs to the
µP will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
TELCOM SEMICONDUCTOR, INC.
Figure 2. Ensuring RESET Valid to V_CC = 0V
5 Processors With Bidirectional I/O Pins
Some µP's (such as Motorola 68HC11) have bidirec-
tional reset pins. Depending on the current drive capability
of the processor pin, an indeterminate logic level may result
if there is a logic conflict. This can be avoided by adding a
4.7k resistor in series with the output of the TCM809/810
(Figure 3). If there are other components in the system
which require a reset signal, they should be buffered so as
6 ^{not to load the reset line. If the other components are}
required to follow the reset I/O of the µP, the buffer should
be connected as shown with the solid line.
V_CC
V_CC
TCM809
RESET
BUFFER
4.7k
V_CC
µP
RESET
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
7
GND
GND
Figure 3. Interfacing to Bidirectional Reset I/O
8
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