73K302L Datasheet, PDF (22/29 Pages) TDK Electronics – Single-Chip Modem

73K302L
Bell 212A, 103, 202
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
TLL
ALE
TLC
TRW
TCL
RD
WR
AD0-AD7
TLA
TAL
ADDRESS
TRD
TRDF
READ DATA
CS
TLC
ADDRESS
TWW
TDW
TWD
WRITE DATA
READ TIMING DIAGRAM (SERIAL MODE)
EXCLK
T1
T2
TRCLK
RD
A0-A2
TAR
TRA
ADDRESS
DATA
TRD
TCKDR
D0
D1
D2
D3
D4
TRDF
D5
D6
D7
WRITE TIMING DIAGRAM (SERIAL MODE)
T2
EXCLK
T1
WR
A0-A2
TWW
TCKW
TAW
TWA
ADDRESS
DATA
TDCK
TCKDW
D0
D1
D2
D3
D4
D5
D6
D7
Note: EXCLK must be Low to read D0 after RD is asserted.
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