XIO2000A_08 Datasheet, PDF (74/159 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
4.32 Power Management Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI power management. See
Table 4−18 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
52h
Read-only
0602h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
BIT
15:11
10
9
8:6
5
4
3
2:0
Table 4−18. Power Management Capabilities Register Description
FIELD NAME ACCESS
DESCRIPTION
PME_SUPPORT
PME support. This 5-bit field indicates the power states from which the bridge may assert PME.
R
Because the bridge never generates a PME except on a behalf of a secondary device, this field
is read-only and returns 00000b.
D2_SUPPORT
R
This bit returns a 1b when read, indicating that the function supports the D2 device power state.
D1_SUPPORT
R
This bit returns a 1b when read, indicating that the function supports the D1 device power state.
AUX_CURRENT
DSI
R
3.3 VAUX auxiliary current requirements. This field returns 000b since the bridge does not
generate PME from D3cold.
Device specific initialization. This bit returns 0b when read, indicating that the bridge does not
R
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
RSVD
R
Reserved. Returns 0b when read.
PME_CLK
R
PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.
PM_VERSION
Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register
R
(offset D4h, see Section 4.65) is 0b, then this field returns 010b indicating revision 1.1
compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating revision
1.2 compatibility.
64 SCPS155C
April 2007 Revised October 2008