XIO2000A_08 Datasheet, PDF (73/159 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
Table 4−17. Bridge Control Register Description (Continued)
BIT FIELD NAME ACCESS
DESCRIPTION
2
ISA
RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to
I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of
PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, then the bridge blocks any
forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each
1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they
address the last 768 bytes in each 1K block.
0 = Forward downstream all I/O addresses in the address range defined by the I/O base and
I/O limit registers (default)
1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base and I/O
limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each
1-KB block)
1
SERR_EN
RW SERR enable. This bit controls forwarding of system error events from the secondary interface to
the primary interface. The bridge forwards system error events when:
• This bit is set
• Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set
• SERR is asserted on the secondary interface
0 = Disable the forwarding of system error events (default)
1 = Enable the forwarding of system error events
0
PERR_EN
RW Parity error response enable. Controls the bridge’s response to data, uncorrectable address, and
attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning,
from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless
of the setting of this bit.
0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface
(default)
1 = Enable uncorrectable address, attribute, and data error detection and reporting on the
secondary interface
4.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. The register
returns 01h when read.
PCI register offset:
Register type:
Default value:
50h
Read-only
01h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
1
4.31 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 60h pointing to the MSI capabilities registers.
PCI register offset:
Register type:
Default value:
51h
Read-only
60h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE 0
1
1
0
0
0
0
0
April 2007 Revised October 2008
SCPS155C
63