CC1110FX Datasheet, PDF (176/240 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller

Writing and reading words for the different
settings is shown in
Figure 44 and Figure 45 respectively. Notice
that the setting for these bits will be used for all
endpoints. Consequently, it is not possible to
have multiple DMA channels active at once
that use different endianness. The ENDIAN
register must be configured to use big endian
CC1110Fx / CC1111Fx
for both read and write for a word size transfer
to produce the same result as a byte size
transfer of an even number of bytes. Word size
transfers are slightly more efficient than byte
transfers.
Refer to section 13.5 for more details
regarding DMA.
Figure 44: Writing Big/Little Endian
Figure 45: Reading Big/Little Endian
13.16.8 USB Reset
When reset signaling is detected on the bus,
the USBCIF.RSTIF flag will be asserted. If
USBCIE.RSTIE is enabled, IRCON2.USBIF
will also be asserted and an interrupt request
is generated if IEN2.USBIE=1. The firmware
should take appropriate action when a USB
reset occurs. A USB reset should place the
device in the Default state where it will only
respond to address 0 (the default address).
One or more resets will normally take place
during the enumeration phase right after the
USB cable is connected.
The following actions are performed by the
USB controller when a USB reset occurs:
• USBADDR is set to 0
• USBINDEX is set to 0
• All endpoint FIFOs are flushed
• USBCS0,
USBCSIL,
USBCSIH,
USBCSOL, USBCSOH are cleared.
• All interrupts, except SOF and suspend,
are enabled
• An interrupt request is generated (if
IEN2.USBIE=1
and
USBCIE.RSTIE=1)
SWRS033E
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