ISD3800FYI Datasheet, PDF (7/25 Pages) Nuvotem Talema – Digital ChipCorder with Digital Audio Interface

ISD3800
5 PIN DESCRIPTION
Pin Pin Name
I/O
Number
48L-
LQFP
1
NC
2
NC
3
NC
4
GPIO7 /
I/O
I²S_SDI
Function
This pin should be left unconnected.
This pin should be left unconnected.
This pin should be left unconnected.
A GPIO pin. By default this pin is a pull-high input.
Can be configured as Serial Data Input of the I²S interface.
5
GPIO6 /
I²S_SCK
6
GPIO5 /
I²S_WS
7
GPIO4 /
I²S_SDO
I/O A GPIO pin. By default this pin is a pull-high input.
Can be configured as Clock input in slave mode or clock output in
master mode. This pin can be configured as an external clock buffer
if I²S is not used.
I/O A GPIO pin. By default this pin is a pull-high input.
Can be configured as Word Select (WS) input in slave mode or WS
output in master mode.
I/O A GPIO pin. By default this pin is a pull-high input.
Can be configured as Serial Data Output of the I²S Interface.
8
NC
9
NC
10
V_SSD
11
V_CCD
12
V_REG
13 MISO /
GPIO1
14 SCLK
15 SSB
16 MOSI /
GPIO0
This pin should be left unconnected.
This pin should be left unconnected.
I Digital Ground.
I Digital power supply.
O A 1.8V regulator to supply the internal logic. A minimum 1uF
capacitor with low ESR<0.5OHM should be connected to this pin for
supply decoupling and stability.
O Master-In-Slave-Out. Serial output from the ISD3800 to the host.
This pin is in tri-state when SSB=1.
Can be configured as GPIO1.
I Serial Clock input to the ISD3800 from the host.
I Slave Select input to the ISD3800 from the host. When SSB is low
device is selected and responds to commands on the SPI interface.
I Master-Out-Slave-In. Serial input to the ISD3800 from the host.
Can be configured as GPIO0.
Publication Release Date: Sep 22, 2010
-7-
Revision 0.60