ISD3800FYI Datasheet, PDF (17/25 Pages) Nuvotem Talema – Digital ChipCorder with Digital Audio Interface

ISD3800
6.3.3 SPI Timing
SSB
SCLK
TSSBS
TSCK
TSCKH
TSCKL
MOSI
TZMID
MISO
RDY/BSYB
TMOS
TMOH
TMID
TCRBD
TSSBHI
TSSBH
TFALL
TRISE
TMIZD
TRBCD
Figure 6-4 SPI Timing
SYMBOL
T_SCK
T_SCKH
T_SCKL
T_RISE
T_FALL
T_SSBS
T_SSBH
T_SSBHI
T_MOS
T_MOH
T_ZMID
T_MIZD
DESCRIPTION
MIN TYP
SCLK Cycle Time
60 ---
SCLK High Pulse Width
25 ---
SCLK Low Pulse Width
25 ---
Rise Time for All Digital Signals
---
---
Fall Time for All Digital Signals
---
---
SSB Falling Edge to 1^st SCLK Falling Edge Setup 30
---
Time
Last SCLK Rising Edge to SSB Rising Edge Hold 30ns ---
Time
SSB High Time between SSB Lows
20 ---
MOSI to SCLK Rising Edge Setup Time
15 ---
SCLK Rising Edge to MOSI Hold Time
15 ---
Delay Time from SSB Falling Edge to MISO Active
--
--
Delay Time from SSB Rising Edge to MISO Tri-state --
--
MAX UNIT
---
ns
---
ns
---
ns
10
ns
10
ns
---
ns
50us ---
---
ns
---
ns
---
ns
12
ns
12
ns
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Publication Release Date: Sep 22, 2010
Revision 0.60