SM8951A Datasheet, PDF (6/17 Pages) SyncMOS Technologies,Inc – 8 - Bit Micro-controller with 4/8KB flash embedded

SyncMOS Technologies Inc.
September 2002
SM8951A/8952A
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
Reset
0
*
value
MSB
0
*
*
0
0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS2 ~ PS0 : clock source divider bit
PS0
0
LSB
PS [2:0]
000
001
010
011
100
101
110
111
Divider (OSC in)
8
16
32
64
128
256
512
1024
Time Period (ms) @40MHZ
13.1
26.21
52.42
104.8
209.71
419.43
838.86
1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
Reset
value
WDR
0
MSB
Unused
*
Unused
*
Unused
*
Unused
*
Unused
*
Unused
*
ALEI
0
LSB
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI
The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8951A/8952A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is
no external program memory or no external data RAM in the system.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/17
Ver 1.0 PID 8951A/8952A 09/02