SM8951A Datasheet, PDF (5/17 Pages) SyncMOS Technologies,Inc – 8 - Bit Micro-controller with 4/8KB flash embedded

SyncMOS Technologies Inc.
September 2002
SM8951A/8952A
SFR Memory MAP
$F8
$F0
B
$E8
$E0
ACC
$D8
$D0 ^PSW
$C8 ^T2CON
$C0
$B8
IP
$B0
P3
$A8
IE
$A0
P2
$98 ^SCON
$90
P1
$88
TCON
$80
P0
SBUF
TMOD
SP
RC2L
TL0
DPL
RC2H
TL2
TH2
TL1
DPH
TH0
TH1
(Reserved)
SCONF
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing
the WDT counter.
The SM8951A/8952A WDT has selectable divider input for the time base source clock. To select the divider input, the set-
ting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The
WDTE bit will be cleared to 0 automatically when SM8951A8952A been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/17
Ver 1.0 PID 8951A/8952A 09/02