SM39R04G1 Datasheet, PDF (39/47 Pages) SyncMOS Technologies,Inc – 4K Bytes on-chip flash program memory

SM39R04G1
8-Bit Micro-controller
4KB with ISP Flash
& 256B RAM embedded
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8^th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
Fig. 11-2: RW bit in the 8^th bit after IIC address
Mnemonic: IICA2
Address: FBh
7
6
5
4
3
2
1
0
Reset
IICA2[7:1]
Match2 or RW2 60h
R/W
R or R/W
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
Mnemonic: IICRWD
Address: FCh
7
6
5
4
3
2
1
0
Reset
IICRWD[7:0]
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
7
6
5
4
3
FU_EN
-
-
-
Address: FDH
2
1
0
Reset
-
-
-
00H
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M053
39
Ver.H SM39R04G1 08/2013